module ALUOut(

        input [31:0] ALU_result,
        input clk,
        output [31:0] ALU_result_out
    );

    reg [31:0] ALUout;

    // Initialize register
    initial begin
        ALUout = 32'd0;
    end

    // Write register
    always @(posedge clk) begin
        ALUout <= ALU_result;
    end

    // Read register
    assign ALU_result_out = ALUout;

endmodule
